Low Loss and Low EMI Noise CSTBT With Split Gate and Recessed Emitter Trench

A novel carrier stored trench bipolar transistor (CSTBT) with split gate (SG) and recessed emitter (SGRET CSTBT) is proposed. The proposed device features a SG structure thicker oxide layer under the emitter, respectively. Compared conventional CSTBT (RET CSTBT), not only significantly reduces gate-collector capacitance ( ${C} _{\mathrm{ GC}}$ ) but also alleviates negative impact of heavily doped n-type on breakdown voltage BV ). Simulation results show that similar about 650V, on-state drop notation="LaTeX">${V} ceon}}$ at notation="LaTeX">${J} ce}}$ =200A/cm 2 for SGRET 1.11V, which 0.19V lower than RET CSTBT. Moreover, compared CSTBT, 25V, total charge notation="LaTeX">${Q} G}}$ miller plateau are reduced by 84.3%, 38.6% 51.6%, As result, trade-off relationship between turn-off loss notation="LaTeX">${E} off}}$ as well turn-on on}}$ notation="LaTeX">$\text{d}{V} ak}} / \text{d}{t}$ free-wheeling diode (FWD) improved device. At same 1.16V, from 9.2mJ/cm one to 3.3mJ/cm 8.3mJ/cm , FWD 24.5% suppresses EMI noise.